

#ifndef _CLOCK_BCM_SR_H
#define _CLOCK_BCM_SR_H


#define BCM_SR_GENPLL0			0
#define BCM_SR_GENPLL0_125M_CLK		1
#define BCM_SR_GENPLL0_SCR_CLK		2
#define BCM_SR_GENPLL0_250M_CLK		3
#define BCM_SR_GENPLL0_PCIE_AXI_CLK	4
#define BCM_SR_GENPLL0_PAXC_AXI_X2_CLK	5
#define BCM_SR_GENPLL0_PAXC_AXI_CLK	6


#define BCM_SR_GENPLL1			0
#define BCM_SR_GENPLL1_PCIE_TL_CLK	1
#define BCM_SR_GENPLL1_MHB_APB_CLK	2


#define BCM_SR_GENPLL2			0
#define BCM_SR_GENPLL2_NIC_CLK		1
#define BCM_SR_GENPLL2_TS_500_CLK	2
#define BCM_SR_GENPLL2_125_NITRO_CLK	3
#define BCM_SR_GENPLL2_CHIMP_CLK	4
#define BCM_SR_GENPLL2_NIC_FLASH_CLK	5
#define BCM_SR_GENPLL2_FS4_CLK		6


#define BCM_SR_GENPLL3			0
#define BCM_SR_GENPLL3_HSLS_CLK		1
#define BCM_SR_GENPLL3_SDIO_CLK		2


#define BCM_SR_GENPLL4			0
#define BCM_SR_GENPLL4_CCN_CLK		1
#define BCM_SR_GENPLL4_TPIU_PLL_CLK	2
#define BCM_SR_GENPLL4_NOC_CLK		3
#define BCM_SR_GENPLL4_CHCLK_FS4_CLK	4
#define BCM_SR_GENPLL4_BRIDGE_FSCPU_CLK	5


#define BCM_SR_GENPLL5			0
#define BCM_SR_GENPLL5_FS4_HF_CLK	1
#define BCM_SR_GENPLL5_CRYPTO_AE_CLK	2
#define BCM_SR_GENPLL5_RAID_AE_CLK	3


#define BCM_SR_GENPLL6			0
#define BCM_SR_GENPLL6_48_USB_CLK	1


#define BCM_SR_LCPLL0			0
#define BCM_SR_LCPLL0_SATA_REFP_CLK	1
#define BCM_SR_LCPLL0_SATA_REFN_CLK	2
#define BCM_SR_LCPLL0_SATA_350_CLK	3
#define BCM_SR_LCPLL0_SATA_500_CLK	4


#define BCM_SR_LCPLL1			0
#define BCM_SR_LCPLL1_WAN_CLK		1
#define BCM_SR_LCPLL1_USB_REF_CLK	2
#define BCM_SR_LCPLL1_CRMU_TS_CLK	3


#define BCM_SR_LCPLL_PCIE		0
#define BCM_SR_LCPLL_PCIE_PHY_REF_CLK	1


#define BCM_SR_EMEMPLL0			0
#define BCM_SR_EMEMPLL0_EMEM_CLK	1


#define BCM_SR_EMEMPLL1			0
#define BCM_SR_EMEMPLL1_EMEM_CLK	1


#define BCM_SR_EMEMPLL2			0
#define BCM_SR_EMEMPLL2_EMEM_CLK	1

#endif 
