

#ifndef _CLOCK_BCM_NS2_H
#define _CLOCK_BCM_NS2_H


#define BCM_NS2_GENPLL_SCR		0
#define BCM_NS2_GENPLL_SCR_SCR_CLK	1
#define BCM_NS2_GENPLL_SCR_FS_CLK	2
#define BCM_NS2_GENPLL_SCR_AUDIO_CLK	3
#define BCM_NS2_GENPLL_SCR_CH3_UNUSED	4
#define BCM_NS2_GENPLL_SCR_CH4_UNUSED	5
#define BCM_NS2_GENPLL_SCR_CH5_UNUSED	6


#define BCM_NS2_GENPLL_SW		0
#define BCM_NS2_GENPLL_SW_RPE_CLK	1
#define BCM_NS2_GENPLL_SW_250_CLK	2
#define BCM_NS2_GENPLL_SW_NIC_CLK	3
#define BCM_NS2_GENPLL_SW_CHIMP_CLK	4
#define BCM_NS2_GENPLL_SW_PORT_CLK	5
#define BCM_NS2_GENPLL_SW_SDIO_CLK	6


#define BCM_NS2_LCPLL_DDR		0
#define BCM_NS2_LCPLL_DDR_PCIE_SATA_USB_CLK	1
#define BCM_NS2_LCPLL_DDR_DDR_CLK	2
#define BCM_NS2_LCPLL_DDR_CH2_UNUSED	3
#define BCM_NS2_LCPLL_DDR_CH3_UNUSED	4
#define BCM_NS2_LCPLL_DDR_CH4_UNUSED	5
#define BCM_NS2_LCPLL_DDR_CH5_UNUSED	6


#define BCM_NS2_LCPLL_PORTS		0
#define BCM_NS2_LCPLL_PORTS_WAN_CLK	1
#define BCM_NS2_LCPLL_PORTS_RGMII_CLK	2
#define BCM_NS2_LCPLL_PORTS_CH2_UNUSED	3
#define BCM_NS2_LCPLL_PORTS_CH3_UNUSED	4
#define BCM_NS2_LCPLL_PORTS_CH4_UNUSED	5
#define BCM_NS2_LCPLL_PORTS_CH5_UNUSED	6

#endif 
