/* SPDX-License-Identifier: (GPL-2.0 OR MIT) */


#ifndef __DT_BINDINGS_IMX8MM_POWER_H__
#define __DT_BINDINGS_IMX8MM_POWER_H__

#define IMX8MM_POWER_DOMAIN_HSIOMIX	0
#define IMX8MM_POWER_DOMAIN_PCIE	1
#define IMX8MM_POWER_DOMAIN_OTG1	2
#define IMX8MM_POWER_DOMAIN_OTG2	3
#define IMX8MM_POWER_DOMAIN_GPUMIX	4
#define IMX8MM_POWER_DOMAIN_GPU		5
#define IMX8MM_POWER_DOMAIN_VPUMIX	6
#define IMX8MM_POWER_DOMAIN_VPUG1	7
#define IMX8MM_POWER_DOMAIN_VPUG2	8
#define IMX8MM_POWER_DOMAIN_VPUH1	9
#define IMX8MM_POWER_DOMAIN_DISPMIX	10
#define IMX8MM_POWER_DOMAIN_MIPI	11

#define IMX8MM_VPUBLK_PD_G1		0
#define IMX8MM_VPUBLK_PD_G2		1
#define IMX8MM_VPUBLK_PD_H1		2

#define IMX8MM_DISPBLK_PD_CSI_BRIDGE	0
#define IMX8MM_DISPBLK_PD_LCDIF		1
#define IMX8MM_DISPBLK_PD_MIPI_DSI	2
#define IMX8MM_DISPBLK_PD_MIPI_CSI	3

#endif
