/* SPDX-License-Identifier: GPL-2.0 */


#ifndef _MACH_T186_CLK_T186_H
#define _MACH_T186_CLK_T186_H




#define TEGRA186_CLK_FUSE 0

#define TEGRA186_CLK_GPU 1

#define TEGRA186_CLK_PCIE 3

#define TEGRA186_CLK_AFI 4

#define TEGRA186_CLK_PCIE2_IOBIST 5

#define TEGRA186_CLK_PCIERX0 6

#define TEGRA186_CLK_PCIERX1 7

#define TEGRA186_CLK_PCIERX2 8

#define TEGRA186_CLK_PCIERX3 9

#define TEGRA186_CLK_PCIERX4 10

#define TEGRA186_CLK_PLLC_OUT_ISP 11

#define TEGRA186_CLK_PLLC_OUT_VE 12

#define TEGRA186_CLK_PLLC_OUT_AON 13

#define TEGRA186_CLK_SOR_SAFE 39

#define TEGRA186_CLK_I2S2 42

#define TEGRA186_CLK_I2S3 43

#define TEGRA186_CLK_SPDIF_IN 44

#define TEGRA186_CLK_SPDIF_DOUBLER 45

#define TEGRA186_CLK_SPI3 46

#define TEGRA186_CLK_I2C1 47

#define TEGRA186_CLK_I2C5 48

#define TEGRA186_CLK_SPI1 49

#define TEGRA186_CLK_ISP 50

#define TEGRA186_CLK_VI 51

#define TEGRA186_CLK_SDMMC1 52

#define TEGRA186_CLK_SDMMC2 53

#define TEGRA186_CLK_SDMMC4 54

#define TEGRA186_CLK_UARTA 55

#define TEGRA186_CLK_UARTB 56

#define TEGRA186_CLK_HOST1X 57

#define TEGRA186_CLK_EMC 58

#define TEGRA186_CLK_EXTPERIPH4 73

#define TEGRA186_CLK_SPI4 74

#define TEGRA186_CLK_I2C3 75

#define TEGRA186_CLK_SDMMC3 76

#define TEGRA186_CLK_UARTD 77

#define TEGRA186_CLK_I2S1 79

#define TEGRA186_CLK_DTV 80

#define TEGRA186_CLK_TSEC 81

#define TEGRA186_CLK_DP2 82

#define TEGRA186_CLK_I2S4 84

#define TEGRA186_CLK_I2S5 85

#define TEGRA186_CLK_I2C4 86

#define TEGRA186_CLK_AHUB 87

#define TEGRA186_CLK_HDA2CODEC_2X 88

#define TEGRA186_CLK_EXTPERIPH1 89

#define TEGRA186_CLK_EXTPERIPH2 90

#define TEGRA186_CLK_EXTPERIPH3 91

#define TEGRA186_CLK_I2C_SLOW 92

#define TEGRA186_CLK_SOR1 93

#define TEGRA186_CLK_CEC 94

#define TEGRA186_CLK_DPAUX1 95

#define TEGRA186_CLK_DPAUX 96

#define TEGRA186_CLK_SOR0 97

#define TEGRA186_CLK_HDA2HDMICODEC 98

#define TEGRA186_CLK_SATA 99

#define TEGRA186_CLK_SATA_OOB 100

#define TEGRA186_CLK_SATA_IOBIST 101

#define TEGRA186_CLK_HDA 102

#define TEGRA186_CLK_SE 103

#define TEGRA186_CLK_APB2APE 104

#define TEGRA186_CLK_APE 105

#define TEGRA186_CLK_IQC1 106

#define TEGRA186_CLK_IQC2 107

#define TEGRA186_CLK_PLLREFE_OUT 108

#define TEGRA186_CLK_PLLREFE_PLL_REF 109

#define TEGRA186_CLK_PLLC4_OUT 110

#define TEGRA186_CLK_XUSB 111

#define TEGRA186_CLK_XUSB_DEV 112

#define TEGRA186_CLK_XUSB_HOST 113

#define TEGRA186_CLK_XUSB_SS 114

#define TEGRA186_CLK_DSI 115

#define TEGRA186_CLK_MIPI_CAL 116

#define TEGRA186_CLK_DSIA_LP 117

#define TEGRA186_CLK_DSIB 118

#define TEGRA186_CLK_DSIB_LP 119

#define TEGRA186_CLK_DMIC1 122

#define TEGRA186_CLK_DMIC2 123

#define TEGRA186_CLK_AUD_MCLK 124

#define TEGRA186_CLK_I2C6 125

#define TEGRA186_CLK_UART_FST_MIPI_CAL 126

#define TEGRA186_CLK_VIC 127

#define TEGRA186_CLK_SDMMC_LEGACY_TM 128

#define TEGRA186_CLK_NVDEC 129

#define TEGRA186_CLK_NVJPG 130

#define TEGRA186_CLK_NVENC 131

#define TEGRA186_CLK_QSPI 132

#define TEGRA186_CLK_VI_I2C 133

#define TEGRA186_CLK_HSIC_TRK 134

#define TEGRA186_CLK_USB2_TRK 135

#define TEGRA186_CLK_MAUD 136

#define TEGRA186_CLK_TSECB 137

#define TEGRA186_CLK_ADSP 138

#define TEGRA186_CLK_ADSPNEON 139

#define TEGRA186_CLK_MPHY_L0_RX_SYMB 140

#define TEGRA186_CLK_MPHY_L0_RX_LS_BIT 141

#define TEGRA186_CLK_MPHY_L0_TX_SYMB 142

#define TEGRA186_CLK_MPHY_L0_TX_LS_3XBIT 143

#define TEGRA186_CLK_MPHY_L0_RX_ANA 144

#define TEGRA186_CLK_MPHY_L1_RX_ANA 145

#define TEGRA186_CLK_MPHY_IOBIST 146

#define TEGRA186_CLK_MPHY_TX_1MHZ_REF 147

#define TEGRA186_CLK_MPHY_CORE_PLL_FIXED 148

#define TEGRA186_CLK_AXI_CBB 149

#define TEGRA186_CLK_DMIC3 150

#define TEGRA186_CLK_DMIC4 151

#define TEGRA186_CLK_DSPK1 152

#define TEGRA186_CLK_DSPK2 153

#define TEGRA186_CLK_I2S6 154

#define TEGRA186_CLK_NVDISPLAY_P0 155

#define TEGRA186_CLK_NVDISPLAY_DISP 156

#define TEGRA186_CLK_NVDISPLAY_DSC 157

#define TEGRA186_CLK_NVDISPLAYHUB 158

#define TEGRA186_CLK_NVDISPLAY_P1 159

#define TEGRA186_CLK_NVDISPLAY_P2 160

#define TEGRA186_CLK_TACH 166

#define TEGRA186_CLK_EQOS_AXI 167

#define TEGRA186_CLK_EQOS_RX 168

#define TEGRA186_CLK_UFSHC 178

#define TEGRA186_CLK_UFSDEV_REF 179

#define TEGRA186_CLK_NVCSI 180

#define TEGRA186_CLK_NVCSILP 181

#define TEGRA186_CLK_I2C7 182

#define TEGRA186_CLK_I2C9 183

#define TEGRA186_CLK_I2C12 184

#define TEGRA186_CLK_I2C13 185

#define TEGRA186_CLK_I2C14 186

#define TEGRA186_CLK_PWM1 187

#define TEGRA186_CLK_PWM2 188

#define TEGRA186_CLK_PWM3 189

#define TEGRA186_CLK_PWM5 190

#define TEGRA186_CLK_PWM6 191

#define TEGRA186_CLK_PWM7 192

#define TEGRA186_CLK_PWM8 193

#define TEGRA186_CLK_UARTE 194

#define TEGRA186_CLK_UARTF 195

#define TEGRA186_CLK_DBGAPB 196

#define TEGRA186_CLK_BPMP_CPU_NIC 197

#define TEGRA186_CLK_BPMP_APB 199

#define TEGRA186_CLK_ACTMON 201

#define TEGRA186_CLK_AON_CPU_NIC 208

#define TEGRA186_CLK_CAN1 210

#define TEGRA186_CLK_CAN1_HOST 211

#define TEGRA186_CLK_CAN2 212

#define TEGRA186_CLK_CAN2_HOST 213

#define TEGRA186_CLK_AON_APB 214

#define TEGRA186_CLK_UARTC 215

#define TEGRA186_CLK_UARTG 216

#define TEGRA186_CLK_AON_UART_FST_MIPI_CAL 217

#define TEGRA186_CLK_I2C2 218

#define TEGRA186_CLK_I2C8 219

#define TEGRA186_CLK_I2C10 220

#define TEGRA186_CLK_AON_I2C_SLOW 221

#define TEGRA186_CLK_SPI2 222

#define TEGRA186_CLK_DMIC5 223

#define TEGRA186_CLK_AON_TOUCH 224

#define TEGRA186_CLK_PWM4 225

#define TEGRA186_CLK_TSC 226

#define TEGRA186_CLK_MSS_ENCRYPT 227

#define TEGRA186_CLK_SCE_CPU_NIC 228

#define TEGRA186_CLK_SCE_APB 230

#define TEGRA186_CLK_DSIC 231

#define TEGRA186_CLK_DSIC_LP 232

#define TEGRA186_CLK_DSID 233

#define TEGRA186_CLK_DSID_LP 234

#define TEGRA186_CLK_PEX_SATA_USB_RX_BYP 236

#define TEGRA186_CLK_SPDIF_OUT 238

#define TEGRA186_CLK_EQOS_PTP_REF 239

#define TEGRA186_CLK_EQOS_TX 240

#define TEGRA186_CLK_USB2_HSIC_TRK 241

#define TEGRA186_CLK_XUSB_CORE_SS 242

#define TEGRA186_CLK_XUSB_CORE_DEV 243

#define TEGRA186_CLK_XUSB_FALCON 244

#define TEGRA186_CLK_XUSB_FS 245

#define TEGRA186_CLK_PLL_A_OUT0 246

#define TEGRA186_CLK_SYNC_I2S1 247

#define TEGRA186_CLK_SYNC_I2S2 248

#define TEGRA186_CLK_SYNC_I2S3 249

#define TEGRA186_CLK_SYNC_I2S4 250

#define TEGRA186_CLK_SYNC_I2S5 251

#define TEGRA186_CLK_SYNC_I2S6 252

#define TEGRA186_CLK_SYNC_DSPK1 253

#define TEGRA186_CLK_SYNC_DSPK2 254

#define TEGRA186_CLK_SYNC_DMIC1 255

#define TEGRA186_CLK_SYNC_DMIC2 256

#define TEGRA186_CLK_SYNC_DMIC3 257

#define TEGRA186_CLK_SYNC_DMIC4 259

#define TEGRA186_CLK_SYNC_SPDIF 260

#define TEGRA186_CLK_PLLREFE_OUT_GATED 261

#define TEGRA186_CLK_PLLREFE_OUT1 262
#define TEGRA186_CLK_PLLD_OUT1 267

#define TEGRA186_CLK_PLLP_OUT0 269

#define TEGRA186_CLK_PLLP_OUT5 270

#define TEGRA186_CLK_PLLA 271

#define TEGRA186_CLK_ACLK 273

#define TEGRA186_CLK_PLL_U_48M 274

#define TEGRA186_CLK_PLL_U_480M 275

#define TEGRA186_CLK_PLLC4_OUT0 276

#define TEGRA186_CLK_PLLC4_OUT1 277

#define TEGRA186_CLK_PLLC4_OUT2 278

#define TEGRA186_CLK_PLLC4_OUT_MUX 279

#define TEGRA186_CLK_DFLLDISP_DIV 284

#define TEGRA186_CLK_PLLDISPHUB_DIV 285

#define TEGRA186_CLK_PLLP_DIV8 286

#define TEGRA186_CLK_BPMP_NIC 287

#define TEGRA186_CLK_PLL_A_OUT1 288

#define TEGRA186_CLK_GPC2CLK 289

#define TEGRA186_CLK_KFUSE 293

#define TEGRA186_CLK_PLLE_PWRSEQ 294

#define TEGRA186_CLK_PLLREFE_REF 295

#define TEGRA186_CLK_SOR0_OUT 296

#define TEGRA186_CLK_SOR1_OUT 297

#define TEGRA186_CLK_PLLREFE_OUT1_DIV5 298

#define TEGRA186_CLK_UTMIP_PLL_PWRSEQ 301

#define TEGRA186_CLK_PEX_USB_PAD0_MGMT 302

#define TEGRA186_CLK_PEX_USB_PAD1_MGMT 303

#define TEGRA186_CLK_UPHY_PLL0_PWRSEQ 304

#define TEGRA186_CLK_UPHY_PLL1_PWRSEQ 305

#define TEGRA186_CLK_PLLREFE_PLLE_PASSTHROUGH 306

#define TEGRA186_CLK_PLLREFE_PEX 307

#define TEGRA186_CLK_PLLREFE_IDDQ 308

#define TEGRA186_CLK_QSPI_OUT 309

#define TEGRA186_CLK_GPCCLK 310

#define TEGRA186_CLK_AON_NIC 450

#define TEGRA186_CLK_SCE_NIC 451

#define TEGRA186_CLK_PLLE 512

#define TEGRA186_CLK_PLLC 513

#define TEGRA186_CLK_PLLP 516

#define TEGRA186_CLK_PLL_P TEGRA186_CLK_PLLP

#define TEGRA186_CLK_PLLD 518

#define TEGRA186_CLK_PLLD2 519

#define TEGRA186_CLK_PLLREFE_VCO 520

#define TEGRA186_CLK_PLLC2 521

#define TEGRA186_CLK_PLLC3 522

#define TEGRA186_CLK_PLLDP 523

#define TEGRA186_CLK_PLLC4_VCO 524

#define TEGRA186_CLK_PLLA1 525

#define TEGRA186_CLK_PLLNVCSI 526

#define TEGRA186_CLK_PLLDISPHUB 527

#define TEGRA186_CLK_PLLD3 528

#define TEGRA186_CLK_PLLBPMPCAM 531

#define TEGRA186_CLK_PLLAON 532

#define TEGRA186_CLK_PLLU 533

#define TEGRA186_CLK_PLLC4_VCO_DIV2 535

#define TEGRA186_CLK_NAFLL_AXI_CBB 564

#define TEGRA186_CLK_NAFLL_BPMP 565

#define TEGRA186_CLK_NAFLL_ISP 566

#define TEGRA186_CLK_NAFLL_NVDEC 567

#define TEGRA186_CLK_NAFLL_NVENC 568

#define TEGRA186_CLK_NAFLL_NVJPG 569

#define TEGRA186_CLK_NAFLL_SCE 570

#define TEGRA186_CLK_NAFLL_SE 571

#define TEGRA186_CLK_NAFLL_TSEC 572

#define TEGRA186_CLK_NAFLL_TSECB 573

#define TEGRA186_CLK_NAFLL_VI 574

#define TEGRA186_CLK_NAFLL_VIC 575

#define TEGRA186_CLK_NAFLL_DISP 576

#define TEGRA186_CLK_NAFLL_GPU 577

#define TEGRA186_CLK_NAFLL_MCPU 578

#define TEGRA186_CLK_NAFLL_BCPU 579

#define TEGRA186_CLK_CLK_32K 608

#define TEGRA186_CLK_CLK_M 609

#define TEGRA186_CLK_PLL_REF 610

#define TEGRA186_CLK_OSC 612

#define TEGRA186_CLK_EQOS_RX_INPUT 613

#define TEGRA186_CLK_DTV_INPUT 614

#define TEGRA186_CLK_SOR0_PAD_CLKOUT 615

#define TEGRA186_CLK_SOR1_PAD_CLKOUT 616

#define TEGRA186_CLK_I2S1_SYNC_INPUT 617

#define TEGRA186_CLK_I2S2_SYNC_INPUT 618

#define TEGRA186_CLK_I2S3_SYNC_INPUT 619

#define TEGRA186_CLK_I2S4_SYNC_INPUT 620

#define TEGRA186_CLK_I2S5_SYNC_INPUT 621

#define TEGRA186_CLK_I2S6_SYNC_INPUT 622

#define TEGRA186_CLK_SPDIFIN_SYNC_INPUT 623


#define TEGRA186_CLK_CLK_MAX 624



#endif
